A RISC-V instruction set architecture (ISA) extensions for neuromorphic computing using minifloats
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Description
Developing a RISC-V instruction set architecture (ISA) extensions for neuromorphic computing in particular for event-based DNNs using minifloats. Recent 8-bit foating-point (minifoat) representations used by DNNs have achieved marginal equivalent accuracy to FP32 foating point precision over different tasks and datasets while providing orders of magnitude reduction in silicon area and power consumption. Minifoats are ideal candidates for neuromorphic computing. The RISC-V core will hand all the maintenance and operations code, perform math operations that the neuromorphic signal processor cannot, and provide various other functions. Essentially, the RISC-V core will serve as a management node for the neuromorphic signal processor. This will greatly ease the use of the neuromorphic signal processor, since it will allow end users with limited knowledge of neuromorphic computing to develop AI applications.
